Hardware Verification with System VERILOG: An Object-Oriented Framework
View more
Hardware Verification with System VERILOG: An Object-Oriented Framework
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog
View more
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog
Verilog HDL 硬件描述语言 第二版 - J. Bhasker 著 徐振林 等译
View more
Verilog HDL 硬件描述语言 第二版 - J. Bhasker 著 徐振林 等译
Verilog HDL: a guide to digital design and synthesis
View more
Verilog HDL: a guide to digital design and synthesis
Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them
View more
Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them
System Verilog验证 测试平台编写指南(第二版)
View more
System Verilog验证 测试平台编写指南(第二版)
Verilog HDL 高级数字设计 Advanced Digital Design with the Verilog HDL
View more
Verilog HDL 高级数字设计 Advanced Digital Design with the Verilog HDL
IEEE Std 1364-2001: Verilog Hardware Description Language
View more
IEEE Std 1364-2001: Verilog Hardware Description Language
Quickstart Practical Guide to Simulation & Synthesis in Verilog
View more
Quickstart Practical Guide to Simulation & Synthesis in Verilog
Verilog HDL Synthesis A Practical Primer
View more
Verilog HDL Synthesis A Practical Primer
搭建你的数字积木 数字电路与逻辑设计(Verilog HDL&Vivado版)
View more
搭建你的数字积木 数字电路与逻辑设计(Verilog HDL&Vivado版)
YO NO CREO EN PRINCIPES AZULES: BILOGIA
View more
YO NO CREO EN PRINCIPES AZULES: BILOGIA
EDA 技术实用教程 VERILOG HDL 版
View more
EDA 技术实用教程 VERILOG HDL 版
Verilog Hardware Description Language. IEEE 1364
View more
Verilog Hardware Description Language. IEEE 1364
EDA技术实用教程——Verilog HDL版(第六版)
View more
EDA技术实用教程——Verilog HDL版(第六版)
FPGA Prototyping by Verilog Examples: Xilinx SpartanTM-3V ersion - Pong P. Chu
View more
FPGA Prototyping by Verilog Examples: Xilinx SpartanTM-3V ersion - Pong P. Chu
The Verilog PLI Handbook: A Users Guide and Comprehensive Reference on the Verilog Programming Language Interface
View more
The Verilog PLI Handbook: A Users Guide and Comprehensive Reference on the Verilog Programming Language Interface